The present invention relates to dynamic random access memory devices and, more particularly, to a dynamic random access memory device which writes/reads data in units of multibits, for example, 8-32 bits.
In a dynamic random access memory (hereinafter referred to as a DRAM for simplifying purposes) having a memory capacity which is increased to replace a plurality of memory chips with a single memory chip to thereby decrease the space where the memory chips are otherwise attached, the memory tends to be accessed in units of multibits. One example of DRAMS where a memory is accessed in units of multibits is U.S. Pat. No. 5,029,330 issued to Kajigaya, Jul. 2, 1991.
In order to access a memory in units of multibits, memory blocks where a pair of memory blocks share a plurality of sense amplifiers, one provided for each of the bit lines, are required to be accessed in units of multibits. In this case, as shown by a geometric layout in FIG. 1 schemed by the present inventors with regard to their development of the present invention, the number of input/output lines I/O1-I/O8 connected via column switches with bit lines with which the memory cells are connected is required to be increased accordingly. When the number of such input/output lines increases, the size of the memory cell array would increase to ensure its wiring area. The respective column switches are controlled by a bit line selection signal delivered from column address decoder to a signal line YS1 or YS2.